1. Field of the Invention
The present invention relates generally to electronic interface operation, and more particularly, to interfaces that are reconfigurable during or after a calibration phase that measures performance of bit-lanes.
2. Description of Related Art
Interfaces within and between present-day integrated circuits have increased in operating frequency and width. In particular, in multiprocessing systems, both wide and fast connections are provided between many processing units. Data width directly affects the speed of data transmission between systems components, as does the data rate, which is limited by the maximum frequency that can be supported by an interface. Calibration routines performed during system initialization, when an interconnect problem is detected, or periodically for maintenance purposes, automatically test the interconnect and may adjust parameters of the interface circuits in order to align bit-lanes and improve overall performance.
Present-day systems interconnect designs may provide fault-tolerance by including spare bit-lanes that are either unused unless needed, i.e., when a failed bit-lane is detected. However, the spare bit-lanes add cost and require physical space to implement. In some systems, spare bit-lanes are used to provide alternate communications paths for information such as checkbits or parity bits.
It is therefore desirable to provide a bus interface that leverages the presence of spare bit-lanes to improve performance and/or reliability of a system that includes the bus interface.